Spudmn's Puma board build

[nitrousnrg]

Any progress around there?

and btw, +1 for missing tooth :-)

[Spudmn]

I have only just got back from a business trip to USA.

My parts have been sitting at the couriers depot so I should have them soon.

More updates to follow soon.

[nitrousnrg]

Cool, keen to know. Good luck!

[Fred]

Keen for updates too!!!! :-)

[Fred]

Spudmn, from the Serial Monitor application note:

If the PLL loses lock during operation, the monitor will fail.

The firmware also doesn't do anything smart with the PLL, though it could, so I just put up an issue on the tracker for that.

It seems as though that's probably what's going on (bad PLL). I'm pretty sure your CPU has the SM inside from what we did together in Dan's lounge, but in the event that it doesn't, I've got one of those $50us units on the way from TA, so I'll let you know how it works out. You need one for any future home build stuff anyway.

Also, I have a pocket DSO quad scope and a saleae logic analyser here, so if you want me to test either my puma or the TA card in any way to compare with what you're seeing, just let me know and I'll try to help you in any way that I can!

I might give you a bell soon from skype and see what you're up to! (If I can find your number!)

Fred.

[Fred]

Spudmn, ECLK will have NO signal on it when the firmware is running and most likely it will have no signal at all times, possibly except while in reset? But probably not even then. I have NO idea how you got 4MHz on there.

See section 22.3.2.13 ECLK Control Register (ECLKCTL) on page 836 for more info. Basically though, with MODA and MODB tied to ground (does PumaS1 even do this??? If not, I think it needs to!) then ECLK is disabled. It should be disabled in the SM too unless otherwise screwed with by the TA crowd or Freescale original. I will check that for you shortly.

Given that we've not got the ability to load new code to it, unless you buy a BDM, we can't load new code with tweaks to the register config that will help you ID this.

However, if you can find MODA and MODB (PE5 & PE6) then you could try some of the other chip modes and see if you can get a clock out of ECLK by doing that. Try anything without a comment after it!

• Special Single-Chip
• Emulation Single-Chip - No ECLK
• Special Test
• Emulation Expanded
• Normal Single-Chip - SHOULD be the default, try configuring to this first in case it's screwing up the rest of everything.
• Normal Expanded

I hope that helps! :-) Back with some SM init info soon.

Fred.

[Fred]

Confirmed! You should not see any oscillations on ECLK with SM or firmware, what goes on during reset, though, no idea, probably nothing. Hence you saw it once and never again. Probe on the wrong trace? Something was wrong when you saw it, not when you didn't. I'd focus your attentions on the other pins that the clocks are on and see what they are doing. Let me know what you want me to test on either my TA or my Puma, happy to help.

[Fred]

I did the PLL calcs today, and spent some time examining the formulas etc and I can conclusively say that these values are wrong.

Marcos

What components should I use on the PLL.

The BOM says 3.3nf 330pF and 3.9K

Your notes on the schematic say 27nf 2.2 nf and 1K

All my boards used:

3.3nF
220pF
3.3kohm

I didn't had the correct values to build the PLL as I wanted (with a sligthy tighter bandwith)

I recommend the standard values as recommended by the freescale engineers:

4.7k Ohm
4.7nF
470pF


I verified these by hand today.

If you had chosen a tighter bandwidth frequency, 14.1566637kHz, in order to come up with 3.3k, then the cap values should have been 11nF and 1.1nF
If you'd chosen an fc of 4.29005401kHz to come up with a value of 1k for the resistor, then the capacitor values would have to be 120nF(0.12uF) and 12nF though this is so far away from the values that freescale recommend (EDIT: "and TA use!" < not true. See later post.) that I'd be extremely reluctant to consider it a good idea.

The above values are just plain wrong. Spudmn, I hope this didn't screw you. Perhaps fix the values you are using and try again.

If you want something done properly, do it yourself. A famous old saying, still in force today.

Fred.

[jharvey]

Sounds like this could be an issue. Fred can you post your math, referencing equations and such? That way others can verify as well. This will allow folks to run the math over a variety of component tolerances, or include the couple pF found in the PCB ect.

[Fred]

All the equations are in the PDF, they look scary, but the reality is that most of them are the same for period, due to our frequency input and output requirements.

It comes down to choosing a bandwidth frequency that is at least 10x lower than 1MHz, recommended to be 50x lower, or about 20kHz. From there you get R, from R and Fc you get C and other C must be between 10 and 20 x smaller than the first one. Quite simple once you get all the un-required terms out of the way.

Fred.