SSPI addresser

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KW1252
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SSPI addresser

Post by KW1252 »

There is no parallel port in MC9S12's pinout, which makes addressing SPI chip enable pins a bit more difficult.

My proposal is to use a SPI "hub", itself a SPI module built out of a serial register with a data line demuxer and a latch. Here's the schematics for it:

Image

First there is the 74xx95 shift register. It's connected into right-shifting mode, at each clock pulse the input signal shift from Qn to Qn+1 and the input signal is written to the Q0.

The output signal is then taken to 74xx154 data selector / demuxer. It's non-synchronous so it needs no clock signal. The chip works by taking in the binary number from A0 to A3 and putting the correspondent data selection line low.

Finally, there's the two (non-synchronous) 74xx373 latching registers. The LE and !OE pins are tied to "addwr" signal, which is like Chip Enable, except in reverse. Normally in SPI device the pin is held low while communicating with the device, here it is pulled high. While the 'addwr' pin is high, the register registers the state of the inputs while keeping the ~OE pin high blanks the outputs. When addwr goes low, the pin latches the signals and enables the output, allowing the data to be received or sent to corresponding module via the SPI lines.

As of now it's only intended as an add-on module so there are pin headers for SPI signal input and throughput, but if the design is incorporated into the board proper, these need to be replaced with sheet pins obviously.
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Fred
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Re: SSPI addresser

Post by Fred »

KW1252 wrote:There is no parallel port in MC9S12's pinout, which makes addressing SPI chip enable pins a bit more difficult.
What exactly do you mean by this? And, before you go and spend a lot (or even a little) time on designing fancy stuff, why not throw the idea around and/or ask the question and/or explain the need for such a thing, first? :-)

So, why do we need to address chip enable pins? Start with the basics! Does SPI not contain some sort of addressing at the core level like CAN does? If not, OK, I understand, but I thought (without reference or foundation) that it did...

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KW1252
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Re: SSPI addresser

Post by KW1252 »

Ah, forget I said anything about a parallel port, my bad.

Okay, basics.

The data bus with CAN-style addressing is I2C. It's a clear-cut case as it only ever needs the three pins to access any module on the bus. It has a lot of benefits like keeping the trace count less, it can be a multi-master system and whatever. On the other hand it does require specifically I2C-chips, and the maximum data rate is 1 MBit/s.

SPI is different. It's very, very low-level communications protocol, it transmits raw bit data between modules through MOSI/MISO lines. There's no message structures or control messages, nor is there addressing. The modules on the bus are addressed only by the Chip Enable signal level; low state means the module is communicated with, high state will make the chip ignore traffic on the bus. The benefit is the bus is very fast (up to 10Mbit/s) and building modules for it can be very simple (like the one here). There are of course a lot of great IC's made to for SPI too.

Right now there are the serial data lines and the clock, but no Chip Enable pins. That won't allow to use more than one SPI circuit, one that's always on. Of course there could be a pin for every module on the SPI but that would be terribly wasteful on I/O resources. Using a demuxer and a few pins as parallel output would be usable, but depending how the MC9S12 handles the ports it may be bothersome if other signals are within the same port; also, youd be pretty much tied to either nibble of the port. I think this is the best way to go for SPI addressing here, as it only takes one pin and is easily expandable without any impact to the rest of the hardware, and it's very likely to have coding benefits as well.
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Re: SSPI addresser

Post by Fred »

So, in summary, you enable it, set it to whatever other device you want, disable it, and write to the other device, then enable it, set it to the next addressable device, then disable, then write to that, etc. ? If so, great :-)
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Re: SSPI addresser

Post by KW1252 »

That's exactly how it's supposed to work :)

The beauty of it it works in perfect accordance to the SPI specification; Chip Enable is an active low, so putting the !CE pin high will cease communication with peripheral devices and makes the address board receive data. At no point needs the logic to be inverted.

A microcontroller could, of course, cut the need of chips to two (The demuxer and the MCU itself) but the use of discrete logic circuits seems more robust here.
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Re: SSPI addresser

Post by KW1252 »

Great news! Going through the schematics I found there actually IS an assigned Chip Enable pin for the MCU, though on the master side it's /SS (Slave Select). No question anymore where to wire the beast, all the pins were right there in the first place!

Also found out there's a chip, MCP23S17, that seems to be doing the same thing my circuit does here. It would reduce the cost and complexity of the board, but I'l have to find out if it keeps the output after deselecting it.

One very obvious use for this is the SD card reader; however, it will need a signal coupler because of the 5/3.3V logic levels.
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Re: SSPI addresser

Post by Spudmn »

KW1252 wrote:
One very obvious use for this is the SD card reader; however, it will need a signal coupler because of the 5/3.3V logic levels.
I have the level shifting circuit under control. When I get back on to the SD card development I will post the circuit.
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Re: SSPI addresser

Post by KW1252 »

I've been thinking about Analog Devices ADUM1201 logic level coupler, which should do the trick too.
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