My proposal is to use a SPI "hub", itself a SPI module built out of a serial register with a data line demuxer and a latch. Here's the schematics for it:
First there is the 74xx95 shift register. It's connected into right-shifting mode, at each clock pulse the input signal shift from Qn to Qn+1 and the input signal is written to the Q0.
The output signal is then taken to 74xx154 data selector / demuxer. It's non-synchronous so it needs no clock signal. The chip works by taking in the binary number from A0 to A3 and putting the correspondent data selection line low.
Finally, there's the two (non-synchronous) 74xx373 latching registers. The LE and !OE pins are tied to "addwr" signal, which is like Chip Enable, except in reverse. Normally in SPI device the pin is held low while communicating with the device, here it is pulled high. While the 'addwr' pin is high, the register registers the state of the inputs while keeping the ~OE pin high blanks the outputs. When addwr goes low, the pin latches the signals and enables the output, allowing the data to be received or sent to corresponding module via the SPI lines.
As of now it's only intended as an add-on module so there are pin headers for SPI signal input and throughput, but if the design is incorporated into the board proper, these need to be replaced with sheet pins obviously.
