DIYEFI.org Forum

Absolutely fantastic work, man! BIG thank you from me! Bang up a new thread in your section regards plan of attack for this, and link it here, please. Or I will :-)

PS, REALLY good to see your focus on, and dedication to, quality control and due process! I appreciate it a LOT and understand the desire to do other things. Great attitude! :-)

So, do we get a full 2.5v hysteresis?

I was wondering why sometimes you're measuring the latency from the falling edge and sometimes the rising edge of the MAX chip's output. Or if there's any difference between the two when the input is a square wave. I think the code is using the rising edge.

the difference is very minimal. see here -> viewtopic.php?f=58&t=1933&p=30270#p30270

I am happy to repeat the tests if people are that concerned that it may be a problem.

Hey Dan,

I think it is great that you performed this testing!

Would you be able to summarize the data captured into a table for easy consumption? I ask because I am having a hard time understanding why configuration (6) is noted as the preferred choice in the related thread.

I went back to the original data that Andy submitted and saw that with the "standard" 10k / 1nF configuration, there was approximately 105us latency on the rising edge and 67us on the falling edge. When he simply removed the 1nF cap, the latency reduced to 0.42us on the rising edge and 0.33us on the falling edge, which would seem to be acceptable.

Thanks,
Huff

No cap == no filtering == unacceptable. Excessive filtering also == unacceptable.

I have looked at this a bit and feel that I have a basic understanding as to what is going on.

Normally (and simply explained), with a differential signal, you have 20k of resistance with a 1nF cap. Using the 1st order filter formula of 1 / (2 x pi x R x C), you have a corner frequency of ~ 8kHz. This means that frequencies some amount above this will be present at both inputs and be cancelled out by the common mode rejection / ignored by the device.

When driven single-ended ( "-" not connected), R basicaly becomes 210k (10k + the device's internal impedance) and you end up with a corner frequency of ~800Hz.

By adding the external 2.5V resistors (1k, 10k, ...?), you effectively reduce R again. I'm pretty sure that you could get the same filtering effect that this configuration results in by merely reducing the cap value of the original configuration to something like 100pF.

I guess you could test this reasoning out by increasing the frequency of the input until the device no longer responds.

Anyway, I agree that a high frequency filter should be present for "noise".

I noticed that the current schematic does not include input cap place holders. Perhaps just placing 0.1 or 0.01uF cap on the input (working against the 1k pull-up) would be sufficient "filtering" even with the removal of the 1nF cap. Or if the 10k on the + input is actually 2 x 5k, then an appropriate cap could be placed between them.

The single-ended to differential drive solution wouldn't be my first choice as any "noise" prior to the conversion would merely propogate to the device.

Hope this makes sense (I was 1/4 beer influenced when I started this reply, now I'm 1/2 : )

Thanks,
Huff

TonyS - some good "food for thought" though. I intend to repeat the tests with rise AND fall time and formulate some sort of report or something that is a bit clearer.

I too have been thinking about filters,etc concerning this device and you have hit the nail on the head with it in regards to the corner frequencies, etc.

Hey Dan,
What I wrote last night still makes some sense to me this morning (thank goodness )
I'd suggest that if you do some more experimentation, that you verify the circuit behaviour at your anticipated maximum frequency (8kHz?) and maybe see what happens at much higher frequencies.
Thanks,
Huff