DIYEFI.org Forum

Following on from the huge smash hit Wake Me Up Before You Go-go everyone's favourite band has released a new track "Wake My Hardware Up Before You Go-go". In this thread of words we learn that in order to get truly high, you have to go way down low!

Both IRQ and XIRQ are level sensitive, though IRQ can be configured to be edge sensitive. In the event that we use XIRQ without the interrupt enabled which I suspect we will, then we need an appropriate voltage level. It would be nice from a code perspective if the signal was consistent, ie, wobbly low voltages won't trigger it and untrigger it continuously (which we could miss with polling).

If the key signal is low voltage (under some threshold that we choose) then the CPU pin should be 5v. When the key signal goes high ("12" volts) then we need to take that pin low to zero volts and leave it there until the key signal goes low again.

Given that we have other mechanism for knowing that it's time to to down, this pin should probably activate with a schmidtt trigger or similar at something like 4v makes cpu go low and 1v makes it go high again. However, thinking about it again, if we do that and for any reason the voltage hangs between our two thresholds, the cpu will never wake up again, or depending on the software perhaps never go to sleep again also.

For the purposes of making sure the power signal is somewhat smooth and consistent we should have two things:

1) a capacitor across the input to smooth things out (perhaps one 10uF tant and one 0.1uF ceramic)
2) a resistor to drain the cap in short order that won't get too hot with continuous 15v applied and won't burn out with continuous 25V applied.

The cap without the resistor would be a terrible idea in case there was only one thing supplied from the relay that triggers this pin (quite likely). The resistor without the cap could result in random voltage swings.

This input pin will feed the BRV divider too, so having a bit of extra filtering on the outside (using the supply wire as a low resistance series resistance for a high cut off RC filter) is a good thing.

If we don't use something like a schmidtt trigger and just use a normal logic gate to invert the signal, then our switch point will depend upon the internal switch point of that device (fed with a zener and rail diodes to cap it) which could vary part to part.

I think I'd prefer the on/off threshold to be around 5v so that random leakage is less likely to appear "on". Whatever happens we don't want the situation where the thing goes to sleep and never wakes up because it went to sleep while the signal was high enough to force the cpu pin low and no transition occurs. Although, at that point it should only be a key on/off cycle away from waking it up, AND, it would only be caused by dodgy wiring anyway. Still, I don't like the idea of not having control of the destiny of the device so perhaps the schmidtt idea is a bad one.

Thoughts?

Fred.

I am probably missing something, but why do we want a low on the IRQ pin (whichever we use) when we apply 12V KEY ON? I feel we may be over-complicating things here and i think we should just stick with our logic high (~+5V) trigger level and just use the input setup in ravage for protecting the cpu pin and do it that way.

Why all the need for this whizz bang stuff? we only want 12V to say 'wake up' and below the logic level threshold for a logic low causing it to 'sleep'. If the user dicks up their wiring, then they dick up the wiring, not a hardware issue IMO.

But as I said, I may be missing something here? I still (after re-reading your post) fail to see why we have to invert our incoming +12V KEY ON signal?

We have to invert it because both pins are "active low" in their default configuration. XIRQ, only, can wake up the device even if all interrupts are masked and the X bit is set. IRQ can be configured to be edge sensitive, but it's missing the wake up no matter what feature that XIRQ has. In the event that you unset the X bit and enable the XIRQ interrupt, it is not maskable and will interrupt other interrupts - this is bad. IRQ is high priority too, I think. I'd strongly prefer to use XIRQ for this task due to the interrupt free wake up call which puts you back where you went to sleep and massively simplifies the code.

Probably just a simple "12v >> cap and drain resistor to ground >> T to BRV circuit >> resistor >> 5.6V zener >> invert logic gate powered from constant 5v > XIRQ pin"

Is sufficient. I'd like to see the cap on the input to the BRV stuff anyway, and when combined with this it needs a drain resistor, well, the BRV circuit will act as a drain resistor in reality, but perhaps not fast enough? Discuss! :-)

Fred.

I need to do my homework about the MCU ISRs, but I'd use IRQ and add some code rather than adding an IC to invert a digital signal.

Maybe a voltage supervisor?

http://search.digikey.com/scripts/DkSea ... NB713CT-ND

These kind of chips have a delay, that could be useful if the analog circuitry needs time time to settle down, but could make thinkgs worse if the CPU is the one whw needs time to be back in charge.

There are variants with adjustable timeout time, different threshold voltages, and there are inverting and non inverting versions. Not sure about how rugged they are to stand harmful votages in the key line.

Microchip have some good supervisory ic's that I have had good success with in the past, but I think the general consensus is to use the XIRQ pin and try it as above?

nitrousnrg wrote:I need to do my homework about the MCU ISRs, but I'd use IRQ and add some code rather than adding an IC to invert a digital signal.

Freescale wrote:IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime

IE, it could put us to sleep, but not wake us up, still need inversion, so inversion is a MUST no matter what we do. That's sorted, discussion about IRQ or XIRQ is still open.

Marcos, given the inversion requirement, how would you achieve that, and what upsides/downsides would it have?

Fred.

The going to sleep can be polled, its not critical. The wake up could be solved with a inverting transistor + capacitor for transient immunity. A zener at the base/gate would be cool for further protection. The 12v from the key would drive the base, and the collector/drain would be pulled up to the constant 5v.

Sounds reasonable?

Right, going to sleep will be polled, no probs. The inversion should be straight forward, I'll leave it up to you, Dan and Jared to argue about the optimal approach for that. The one feature that it needs is a known (and possibly tunable if required) voltage switch point on its input. The LDO drop out voltage is probably a good choice, but any other fixed point with some crossing stability is also good (even if its just a small cap or RC filter).

Yes, sounds reasonable. Dan, you're in charge for your impl, what say you?

Fred.

will update tonight/tomorrow evening.

Dan, will this part, which I can get locally for a few cents, be a suitable test chip for the wake-up stuff? 74LS05

It appears to have a switch point of 1.5V or so. That appears to be the case for the single gate part that you chose, too.

If I get one of these and some basic soldering gear and so on, I can do some tests on the bench and maybe even play with adding some wake-up/go to sleep code wrapped in an ifdef.

Ravage has 0.32uF of capacitance on the switched 12V input and 4.9k to charge and 1k to drain it with 12v floating, how fast will it drain? This seems wrong in RavAGE all of a sudden. It would seem more appropriate to have a resistor across the zener and a capacitor there too such that the drain time can be tuned independently of the BRV filtering which has different requirements. Clearly the BRV stuff will attempt to hold it high even if we try to drain faster, however a V divider network will be formed by the 1k, 3.9k and whatever we use on the switch side (2 more resistors) and if they are lower value, they'll pull the value lower than the voltage on the BRV pin before it fully discharges.

I'll also need caps and resistors to simulate this effect: 1k, 3.9k, ?k, 5.6V zener, 470ohm*2, 0.22uF, 0.1uF, schottky

For testing I can not put the micro to sleep and watch the BRV fall in real time as the power goes away from it to see the profile over time with those values. I can also hook another pin to the sleep input connection and watch that voltage and see what it does. If we have sufficient impedance then noise won't be an issue, but rise/fall times could be.

OK, enough thinking about this, it's time for some practical experimentation now. Let me know if that part is OK to prove the point, or not.

Fred.