Here's the reference design from the datasheet:
It looks pretty neat, the only problem is it's designed for 4-layer PCB and the bottom layer is supposed to be untouched ground plane. However, I think we're going to need only one LDO output, so the traces on bottom layer will remain very small and long traces across the zone are not needed.
As for the simulation, well that doesn't look too pretty yet. The reference design yielded this v/t graph:
The 0.15mV ripple doesn't look bad, but that 1mV sawtooth does. I'll test a bit more and see if some caps and inductors will make it behave better.