XGATE + S12X Concurrency Issues

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SleepyKeys
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

Nice find. CodeWarriro seems to behave like that by default. I'll have to see what GCC does by default.
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

GCC will generate this with the current FreeEMS Makefile:

Code: Select all

	; Begin inline assembler code
#APP
	nop
; End of inline assembler code
#NO_APP
	std	_.z
	stx	_.xy
	ldx	_.z
	bset	0,x, #1
	ldx	_.xy
	bclr	1, #-2
; Begin inline assembler code
#APP
	nop
; End of inline assembler code
#NO_APP
from this C source:

Code: Select all

asm volatile ("nop");
PORTA |= 0x01;
PORTB &= 0x01;
asm volatile ("nop");
Note that I used different ports to avoid possible optimization because the instructions are so close together.
[edit]
I should probabbly note that my gcc asm is from the generated source file and not a dump of the s19.
[/edit]
Last edited by SleepyKeys on Thu Mar 29, 2012 5:27 pm, edited 1 time in total.
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

CodeWarrior's spit....

C input:

Code: Select all

 PORTA |= 0x01;
 PORTB &= 0x01;
asm generated:

Code: Select all

   0004 4c0001       [4]     BSET  _PORTAB,#1
   0007 4d00fe       [4]     BCLR  _PORTAB:1,#254
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Fred
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Re: XGATE + S12X Concurrency Issues

Post by Fred »

I just checked some ISR code and got a reminder of how to avoid that. You don't |= interrupt flag registers you just plain set them with =. So it's not an issue, then. There shouldn't be conflicts with S12 to S12 according to this, but XGATE is still an issue as we could sneak in and change the game part way through your instruction set.
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

Oh yeah thats right. I do the same with XG.
LDL R2, #PIT1_CFLAG_MASK
LDD R3, #PITTF
STB R2, R3, #ZERO_OFFSET
I guess that's partly because it's the only thing I can do ?? LOL

A semaphore is the only right way to do it. If the write/read instructions manage to colide both cores hard lock.

-Sean
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Re: XGATE + S12X Concurrency Issues

Post by Fred »

Sean0 wrote:If the write/read instructions manage to colide both cores hard lock.
Please list your reference.
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

It was an observation I made when I was working with it in *unsafe ways. I'll see what refs I can find though.
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Re: XGATE + S12X Concurrency Issues

Post by Fred »

I think that it's a false observation. If both cores desire access, S12 wins. Define "unsafe"?
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Re: XGATE + S12X Concurrency Issues

Post by SleepyKeys »

Fred wrote:I think that it's a false observation. If both cores desire access, S12 wins. Define "unsafe"?
I belive you're thinking of requesting access to a hardware semaphore. Im talking about reading/writing to a *shared register without a condom on.
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Re: XGATE + S12X Concurrency Issues

Post by Fred »

Sean0 wrote:Im talking about reading/writing to a shared register without a condom on.
LOL! No, I was talking about when you had some instructions misaligned at some point and it locked up. Considering the manual states that S12 takes precedence if two accesses occur at the same time, I'll require some pretty hard evidence (not circumstantial) to believe otherwise :-)
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