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Arttu's MS3 compatible processor board 
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LQFP144 - On Top Of The Game
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Thanks for the clarification Fred :)

I tend to design something, work out the bugs then move on to the next part of the design that needs improvement. Normally I take notes and add those to the schematics or to the TODO list, but those 10uF caps were something that Fred and I discussed 2 years ago when I started working on the Jaguar schematics.

Arttu wrote:
Thanks for comments.

You are welcome.

Arttu wrote:
Apparently we have slightly different point of view to using schematics ;) I'm using it to just define logical connections i.e. which pin connects to which net and so on. Signal routing is completely up to layout phase.

Yeah, I tend to make the schematics as clear as possible and to include notes as to why some things are drawn the way they are or if some components are not necessary for a particular application or if they should be different values.

Your method may work for you, if you remember in what order the trace routing should occur. I tend to make that clear in my schematics. This makes it easier for someone else to follow what is being accomplished.

Arttu wrote:
So even though some power supply/ground pins are connected together before the capacitors in the schematic on the board each pin pair has own decoupling cap in close proximity.

Good to know that you did that, but since the only things you have shared so far are the schematics and the component placement diagrams the people (including myself) reviewing your idea can't see that is what you did. I would recommend sharing the trace routing as well so we can see that you have the ground plane and Vcc connections correct.

Arttu wrote:
There is a couple of 10uF bulk capacitors on the VCC net but they are located a bit further from the processor. It might be a good idea to add more of these and place them closer to the processor. For battery voltage fluctuations there is more capacitance on the main board.

This *might* be ok, without seeing what modifications you have made to the board you are plugging this into, I can't comment one way or the other...

Arttu wrote:
I have to admit that I intentionally omitted that star shaped grounding scheme suggested on the datasheet ;) I'm using four layer board and both GND and VCC have their own layers with almost continuous planes. Each supply and ground pin is connected to the plane as close as possible.

You may run into noise on your power supply to the MCU or even having the MCU reset when it shouldn't or at a time that could be catastrophic to your engine... This may be a good test on the bench, but I'm not sure I would put it in the engine compartment and expect it to be OK.

Arttu wrote:
At the moment the PCBs are on the way from factory to me. So let's see how they work. If they have any noticeable issues I'll fix them for the next revision.

OK, keep us in the loop in the future before you place the PCB order so we can go through the design to weed out possible gotchas.
8-)

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Fri Sep 19, 2014 11:30 pm
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Arttu, the under-CPU connections are irrespective of other planes and so forth, it's still wise to follow them even with 4+ layers. Dropping down to the plane willy nilly seems nice, but isn't correct.

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Fri Sep 19, 2014 11:36 pm
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Thanks for the comments, Andy.

There seems to be some paging differences; the power pin discussions in the datasheet I have are on p65-67, while the 112-pin PCB layout is on p1297. A brief moment of confusion, but nothing critical. :)

Good point on Vdd1 and 2; I'm not used to uP with their own inboard VRs.

2-layer or 4, I'd be dropping vias to Vcc - I've found it easiest to have the SMD components on the ground side of a 2-layer board. Reading AN3262, on a 4-layer I assume you'd locate the ground via(s) just inboard of Vssr. Actually - just looking again at your Jaguar layout, I see you have individual traces coming off the various 'external' ground pins to vias away well away from the under-chip plane. Doesn't that rather defeat the purpose of the star layout?

From AN3262 - "If not using a full board ground plane, connect the ground pins in a star arrangement with the central point of the ground star at the VSSR pin. Where there is a full board ground plane, connect all VSS supplies directly to the plane, except for VSSPLL and the
oscillator circuit ground." You have the star, but it's connected to various traces to vias.

Am I overthinking this?

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Sat Sep 20, 2014 8:54 am
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Fred wrote:
The big caps up close are not for battery fluctuation, they're for IO suppression. IE, when the CPU switches loaded pins rapidly, it's these caps that help ensure there is a stable supply still available for *everything else*. Clearer? :-)

I know quite well what's the purpose of decoupling capacitors :)


Sun Sep 21, 2014 8:44 am
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Regarding ground / power supply connections and layout. I can believe that this star-like grounding suggested in the datasheet is better than direct connections to a solid ground plane. But I slightly doubt if the difference is significant in real world if we are talking about multilayer boards with proper ground and power supply planes. Short via connections to a solid ground plane is very widely used practice among the industry and it's recommended on many datasheets of very similar microcontrollers like this Freescale one.

So I'm quite confident this lay-out will work just fine. However, I'm going to evaluate it with open eyes and if I or someone else notices any problems with it I can admit that and fix the problems.

I'll print out some layout/routing pictures and post them here. I just need to figure out how to get understandable result out of the layout. If I just print out all the layers it will be quite difficult to see anything meaningful from them :)


Sun Sep 21, 2014 9:11 am
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I wasn't describing decoupling capacitors, really, I was describing local reservoir capacitors. Nomenclature, sure, but... in any case, I was correcting Andy, not trying to patronise you, so it'd be nice if you didn't act like I had been ;-)

If looking at Jag, make sure you're looking at the right version/branch. ALL older Jag releases had really bad under-CPU layout. Only the latest has this fixed.

@Dontz, you missed a bit of the quote: "Connect VSSPLL directly to VSSR (maintaining the star layout)." however thanks for the reference.

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Sun Sep 21, 2014 10:06 am
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Re posting PDFs, which package are you using and what is your intended licensing? Why not put up a git repo with the original files and allow people to review using the real tools? Just a thought. Or at least be clear about why you're not doing that.

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Sun Sep 21, 2014 10:10 am
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Fred wrote:
I wasn't describing decoupling capacitors, really, I was describing local reservoir capacitors. Nomenclature, sure, but... in any case, I was correcting Andy, not trying to patronise you, so it'd be nice if you didn't act like I had been ;-)

Sorry, I didn't mean it that way.

As general note, English isn't my native language and quite often I have difficulties to word out what I want to say. So if my writings happen to sound rude or awkward it's most likely due to that, not intentional.

Quote:
Re posting PDFs, which package are you using and what is your intended licensing? Why not put up a git repo with the original files and allow people to review using the real tools? Just a thought. Or at least be clear about why you're not doing that.


Package, do you mean design SW tools? I'm using PADS. I'm not sure if publishing the actual design files would be very useful since people are using different tools so most of people here couldn't use them any way. I'm not familiar with git so setting that up would require some effort and I'm not sure what extra value it would provide for anyone. But I can consider that if it is seen useful for the community :)

I haven't thought much about licensing from formal point of view, yet. On general level all the documents that I publish are free to use by anyone and any way they like. The first goal of this project is to get myself and maybe some friends experimenting with the FreeEMS. Later on if the board proves itself functional and useful I may provide them for sale for reasonable price. I hope this sounds acceptable?


Mon Sep 22, 2014 6:52 am
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OK, no worries. I'm a bit short on sleep right now, so excuse the pointedness of my writings.

Re licensing, I don't mind what you do, but I strongly feel that it's important to be clear and up front about it. If you want to promote maximum free use for profit or sharing, MIT is a good choice. If you call it non-free (all rights reserved or similar) now, you can always extend freedoms later. If you make it very free now, you can always close it up later, too. Usual stuff applies :-)

You're probably right about the cost/benefit ratio of sharing PADS design files here :-)

Fred.

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Tue Sep 23, 2014 4:05 am
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As promised here are some pictures about layout and routing. First the raw data:
component placement, top
component placement, bottom
copper, layer 1
copper, layer 2
copper, layer 3
copper, layer 4

And a couple of screenshots that are hopefully a bit easier to read.

Top routing, VCC and GND nets highlighted.
Image

Bottom routing, again VCC and GND nets highlighted.
Image

And all that printed on FR4 :lol:
Image


Tue Sep 23, 2014 7:44 pm
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