Re: Arttu's MS3 compatible processor board
Posted: Mon Sep 15, 2014 6:56 am
Thanks for the schema! So you have already tested this on bench but not on any engine?
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This minimizes noise and it keeps the trace resistance low as well as minimizes the chance of a ground loop. This is also the recommended layout from Freescale, they have engineers who have written application notes on why this is done the way it is, see their AppNotes for further explanation.DonTZ125 wrote:I've just looked at the recommended layout in the datasheet - what a fascinating arrangement. I'm still very much learning the ins and outs of decoupling caps and ground planes etc, and I have to ask - why is there a 'star' arrangement inside a ground plane?
I think you are referring to the 144pin recommended layout versus the 112pin recommended layout since C11 doesn't exist on page 1295 (112 pin MCU which is what the Jaguar PCB and Arttu's PCB are using). Note that on the 112pin MCU, C1 and C2 are for the outputs of the internal +2.5v voltage regulator and there should be no other connection to VDD1 or VDD2. See my previous answer for the ground path question.DonTZ125 wrote:Is the affect of C1, C6, and C11 on each other really that great that the ground paths have to be separated?
Any vias to the ground plane should be made prior to the VDDR/VSSR MCU pins, this should be the only connection to the ground plane for the MCU circuit according to Freescale. See my docs directory in my Jaguar repository: https://github.com/DeuceEFI/Jaguar/tree/0.7-alpha/docs, the Jaguar-0.7-alpha-*.pdf files and the Jaguar-0.7-alpha-*.png files will give you an example of this.DonTZ125 wrote:I assume vias to the main ground plane are there in spirit ...
Again, C1 (VDD1/VSS1) and C2 (VDD2/VSS2) should have no connections other than to their capacitors. These are the outputs from the internal MCU +2.5v voltage regulator and only the capacitor should be connected between these pins, you never want to connect the VDD bus to VDD1 or VDD2 or damage to the MCU WILL occur.DonTZ125 wrote:The datasheet shows a Vdd bus that wraps around the processor. What would be gained / lost by using individual vias to the Vcc plane, much as what I assume C1 is using?
DonTZ125 wrote:Andy - you mentioned 10uF bulk caps on VDDR1 and VDDX; the data sheet simply recommends caps larger than 100nF (0.1uF). How/why did you select 10uF?
No worries, we are all here to learn something from everyone else.DonTZ125 wrote:No criticism implied; looking to learn from someone who obviously has more of a clue than I do!
Thanks for comments. Apparently we have slightly different point of view to using schematics I'm using it to just define logical connections i.e. which pin connects to which net and so on. Signal routing is completely up to layout phase. So even though some power supply/ground pins are connected together before the capacitors in the schematic on the board each pin pair has own decoupling cap in close proximity.DeuceEFI wrote:Arttu,
You need to have a closer look at the Jaguar schematic (https://github.com/DeuceEFI/Jaguar/blob ... ematic.pdf) and pay attention to the capacitor placement and connections to the micro-controller.Once you have the above items corrected, the next suggestion I have for you would be to also post a link to the trace layout along with the component placement diagrams as routing is where most of the mistakes will be made. I would say that placement is the easy and quick part of the design process, the routing of the traces will be where you spend the most time and will be the difference between a design that sort of works (and has issues) versus one that is world class.
- You are missing the larger 10uF bulk capacitors on VDDR1 and VDDX, instead you have these on VDD1 and VDD2 which don't require the bulk capacitors.
- You have combined the VDDX, VDDR1 and VDDA inputs and all of the VSS inputs rather than keeping them separate, again look over the Jaguar schematic.
- Make sure you keep the 0.22uF bypass capacitors close to their respective VDD/VSS pins.
- Make sure you keep the 0.22uF bypass capacitor close to the VRH/VRL pins.
- When you supply power and ground to the MCU make sure you supply +5v to VDDA and ground to VSSA according to the Freescale MC9S12XDP512RMV2 datasheet, specifically see page 1292 for their recommendations for the power supply connections and page 1295 for the recommended trace/component layout.