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Arttu's MS3 compatible processor board 
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DIP8 - Involved

Joined: Mon Dec 10, 2012 10:10 am
Posts: 19
Thanks for the schema! So you have already tested this on bench but not on any engine?


Mon Sep 15, 2014 6:56 am
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DIP8 - Involved

Joined: Mon Dec 10, 2012 10:10 am
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Changes to the lay-out are done and component placement pictures on previous links are updated.


Mon Sep 15, 2014 7:26 am
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QFP80 - Contributor

Joined: Sun Apr 14, 2013 8:50 am
Posts: 34
Location: Australia
Arttu,
If space permits, is it possible to bring the remaining unused mcu pins out to a new header?
That way the board would be future proof. If someone needed extra CAN channels or SPI etc. they could be tapped and linked down to the baseboard application without affecting the M$3 compatibility.

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Mon Sep 15, 2014 7:40 am
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DIP8 - Involved

Joined: Mon Dec 10, 2012 10:10 am
Posts: 19
Most of the unused IO pins are already routed to test points so they are quite easily available if needed. Routing them to a single header would be slightly complicated as the space is limited. I'm prepared to spin out new revision(s) as the firmware side develops further and stabilizes so I think future IO pin use cases can be addressed better at that point.


Mon Sep 15, 2014 9:26 am
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QFP80 - Contributor

Joined: Sun Apr 14, 2013 8:50 am
Posts: 34
Location: Australia
Excellent, Test points will do nicely! :)
The reason I mentioned it is we use two can channels in our XEP100 based applications, 500k engine and 100k body, so the RTC pins 98/99 can be repurposed, but alternatives are nice to have.

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Mon Sep 15, 2014 9:42 am
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LQFP144 - On Top Of The Game
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Joined: Thu Feb 25, 2010 3:57 am
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Location: Gosport, IN USA
Arttu,

You need to have a closer look at the Jaguar schematic (https://github.com/DeuceEFI/Jaguar/blob/0.7-alpha/docs/Jaguar-0.7-alpha-Schematic.pdf) and pay attention to the capacitor placement and connections to the micro-controller.
  • You are missing the larger 10uF bulk capacitors on VDDR1 and VDDX, instead you have these on VDD1 and VDD2 which don't require the bulk capacitors.
  • You have combined the VDDX, VDDR1 and VDDA inputs and all of the VSS inputs rather than keeping them separate, again look over the Jaguar schematic.
  • Make sure you keep the 0.22uF bypass capacitors close to their respective VDD/VSS pins.
  • Make sure you keep the 0.22uF bypass capacitor close to the VRH/VRL pins.
  • When you supply power and ground to the MCU make sure you supply +5v to VDDA and ground to VSSA according to the Freescale MC9S12XDP512RMV2 datasheet, specifically see page 1292 for their recommendations for the power supply connections and page 1295 for the recommended trace/component layout.

Once you have the above items corrected, the next suggestion I have for you would be to also post a link to the trace layout along with the component placement diagrams as routing is where most of the mistakes will be made. I would say that placement is the easy and quick part of the design process, the routing of the traces will be where you spend the most time and will be the difference between a design that sort of works (and has issues) versus one that is world class.
;)

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Fri Sep 19, 2014 1:16 am
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QFP80 - Contributor

Joined: Tue Feb 12, 2013 5:43 am
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Location: Scarborough, ON
I've just looked at the recommended layout in the datasheet - what a fascinating arrangement. I'm still very much learning the ins and outs of decoupling caps and ground planes etc, and I have to ask - why is there a 'star' arrangement inside a ground plane? Is the affect of C1, C6, and C11 on each other really that great that the ground paths have to be separated? If so, why not use discrete ground traces between those pins and a smaller central plane in the middle of the chip? I assume vias to the main ground plane are there in spirit ...

The datasheet shows a Vdd bus that wraps around the processor. What would be gained / lost by using individual vias to the Vcc plane, much as what I assume C1 is using?

Andy - you mentioned 10uF bulk caps on VDDR1 and VDDX; the data sheet simply recommends caps larger than 100nF (0.1uF). How/why did you select 10uF? No criticism implied; looking to learn from someone who obviously has more of a clue than I do! ;)

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Fri Sep 19, 2014 12:36 pm
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DonTZ125 wrote:
I've just looked at the recommended layout in the datasheet - what a fascinating arrangement. I'm still very much learning the ins and outs of decoupling caps and ground planes etc, and I have to ask - why is there a 'star' arrangement inside a ground plane?

This minimizes noise and it keeps the trace resistance low as well as minimizes the chance of a ground loop. This is also the recommended layout from Freescale, they have engineers who have written application notes on why this is done the way it is, see their AppNotes for further explanation.

DonTZ125 wrote:
Is the affect of C1, C6, and C11 on each other really that great that the ground paths have to be separated?

I think you are referring to the 144pin recommended layout versus the 112pin recommended layout since C11 doesn't exist on page 1295 (112 pin MCU which is what the Jaguar PCB and Arttu's PCB are using). Note that on the 112pin MCU, C1 and C2 are for the outputs of the internal +2.5v voltage regulator and there should be no other connection to VDD1 or VDD2. See my previous answer for the ground path question.

DonTZ125 wrote:
I assume vias to the main ground plane are there in spirit ...

Any vias to the ground plane should be made prior to the VDDR/VSSR MCU pins, this should be the only connection to the ground plane for the MCU circuit according to Freescale. See my docs directory in my Jaguar repository: https://github.com/DeuceEFI/Jaguar/tree/0.7-alpha/docs, the Jaguar-0.7-alpha-*.pdf files and the Jaguar-0.7-alpha-*.png files will give you an example of this.

DonTZ125 wrote:
The datasheet shows a Vdd bus that wraps around the processor. What would be gained / lost by using individual vias to the Vcc plane, much as what I assume C1 is using?

Again, C1 (VDD1/VSS1) and C2 (VDD2/VSS2) should have no connections other than to their capacitors. These are the outputs from the internal MCU +2.5v voltage regulator and only the capacitor should be connected between these pins, you never want to connect the VDD bus to VDD1 or VDD2 or damage to the MCU WILL occur.

On the other hand VDDR1, VDDX and VDDA can be vias to the Vcc plane if using a PCB design with more than 2 layers, just make sure to supply Vcc to the capacitors first, then the MCU pins. Keep in mind the Jaguar design is a 2 layer PCB.

DonTZ125 wrote:
Andy - you mentioned 10uF bulk caps on VDDR1 and VDDX; the data sheet simply recommends caps larger than 100nF (0.1uF). How/why did you select 10uF?

VDDR1/VSSR1 and VDDX/VSSX are the power supply inputs to the internal voltage regulators within the MCU. I used the 10uF bulk capacitors to prevent the MCU from resetting while the engine is cranking due to the supply voltage to the PCB being drawn down close to the lower input limit of the external 5v voltage regulator that supplies +5v to the MCU. This condition occurs when the battery is weak or if the starter draws the battery voltage down while trying to start the engine. The 5v voltage regulators have 10uF and 47uF capacitors on their inputs/outputs as well.

DonTZ125 wrote:
No criticism implied; looking to learn from someone who obviously has more of a clue than I do! ;)

No worries, we are all here to learn something from everyone else. :)

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Andy.
FreeEMS vehicle #11, 1932 Ford 5 Window Coupe with a 1996 GM 3.1L SFI V6 with DIS ignition
FreeEMS vehicle #16, 1996 Chevrolet S10 2.2L SFI I4 with DIS ignition
http://www.coolefi.com


Fri Sep 19, 2014 2:33 pm
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DIP8 - Involved

Joined: Mon Dec 10, 2012 10:10 am
Posts: 19
DeuceEFI wrote:
Arttu,

You need to have a closer look at the Jaguar schematic (https://github.com/DeuceEFI/Jaguar/blob/0.7-alpha/docs/Jaguar-0.7-alpha-Schematic.pdf) and pay attention to the capacitor placement and connections to the micro-controller.
  • You are missing the larger 10uF bulk capacitors on VDDR1 and VDDX, instead you have these on VDD1 and VDD2 which don't require the bulk capacitors.
  • You have combined the VDDX, VDDR1 and VDDA inputs and all of the VSS inputs rather than keeping them separate, again look over the Jaguar schematic.
  • Make sure you keep the 0.22uF bypass capacitors close to their respective VDD/VSS pins.
  • Make sure you keep the 0.22uF bypass capacitor close to the VRH/VRL pins.
  • When you supply power and ground to the MCU make sure you supply +5v to VDDA and ground to VSSA according to the Freescale MC9S12XDP512RMV2 datasheet, specifically see page 1292 for their recommendations for the power supply connections and page 1295 for the recommended trace/component layout.
Once you have the above items corrected, the next suggestion I have for you would be to also post a link to the trace layout along with the component placement diagrams as routing is where most of the mistakes will be made. I would say that placement is the easy and quick part of the design process, the routing of the traces will be where you spend the most time and will be the difference between a design that sort of works (and has issues) versus one that is world class.
;)

Thanks for comments. Apparently we have slightly different point of view to using schematics ;) I'm using it to just define logical connections i.e. which pin connects to which net and so on. Signal routing is completely up to layout phase. So even though some power supply/ground pins are connected together before the capacitors in the schematic on the board each pin pair has own decoupling cap in close proximity.

There is a couple of 10uF bulk capacitors on the VCC net but they are located a bit further from the processor. It might be a good idea to add more of these and place them closer to the processor. For battery voltage fluctuations there is more capacitance on the main board.

I have to admit that I intentionally omitted that star shaped grounding scheme suggested on the datasheet ;) I'm using four layer board and both GND and VCC have their own layers with almost continuous planes. Each supply and ground pin is connected to the plane as close as possible.

At the moment the PCBs are on the way from factory to me. So let's see how they work. If they have any noticeable issues I'll fix them for the next revision.


Fri Sep 19, 2014 6:38 pm
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The big caps up close are not for battery fluctuation, they're for IO suppression. IE, when the CPU switches loaded pins rapidly, it's these caps that help ensure there is a stable supply still available for *everything else*. Clearer? :-)

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Fri Sep 19, 2014 11:21 pm
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