So I threw a scope at the mighty hotel input and output of input and found that it's pretty fucked :-)
First screenshot, near idle
Time of a cylinder cycle: 7.6 * 5 = 38ms
Time of a revolution: 2 * 38 = 76ms
Engine speed in RPM: 60000 / 76 = 789.473684211
Lag of leading edge: 1.6 * 5 = 8ms
Lag of trailing edge: WTF
Could this be lagging by an entire cycle or more? :-o Or am I missing something?
Second screenshot, high idle
Time of a cylinder cycle: 7.9 * 2 = 15.8ms
Time of a revolution: 2 * 15.8 = 31.6ms
Engine speed in RPM: 60000 / 31.6 = 1898.73417722
Lag of leading edge: ?
Lag of trailing edge: ?
/me is completely baffled
Third screenshot, medium revs
Time of a cylinder cycle: 8.8 * 1 = 8.8ms
Time of a revolution: 2 * 8.8 = 17.6ms
Engine speed in RPM: 60000 / 17.6 = 3409.09090909
Lag of leading edge: ?
Lag of trailing edge: ?
Yep, /me is puzzled.
In any case, an asymmetrical input circuit is 100% not OK. So the plan, then:
- 5V power to hall setup (currently 12V, may be necessary, to be experimented with)
- 5V pull up on input of maximum strength (currently 12V including possible spikes)
- Small capacitor for rapid charge/discharge and some noise immunity (currently has 102/1nf on it)
- Schmidt trigger IC with hysteresis, same as Dan has used in his skybucket ECU (currently has a dirty slow opto in it)
This should:
Provide fast reliable honest noise-immune input that allows the engine to run as it did way back in 2010? Or when ever I got it running. As bad as the Puma is/was, it did a better job than a shitty 4n25 opto a la Mega$quirt :-)
May drive it despite all of this, as below 3k it seems reasonable.
Fred.