To me it appears that the FB pin may have a problem. I'm a bit ignorant about exactly what the FB pin does. Seems the reference schematic's will either connect it to Vout (allowing an analog output) or to a pot wiper that ranges from Vref to gnd (allowing for a digital out at a set point). As drawn, it's hardwired to Vref, which the wiper will allow. This seems to put it in "set point" mode which I think will cause the output to go low when just under 500C and go +5 at just over 500C. However it may induce an offset instead, such that the full scale might not require the 12V supply. I believe it will want to be connected to that 12V. I guess time will tell. I feel the datasheet is vague relative to the FB pin. If worst comes to worst, lead 5 can be lifted and have a wire soldered directly to it. Also the 5V line can be broken and attached to 12V via jumper if required. Perhaps Macro's will want to lightly drill the top of the via under the AD597 chip, breaking the 5V supply trace. It's easy to break this connection before the chip is installed, but will require removing the chip after it's installed.jbelanger wrote:it's not a mix of modes but it a mix of pins between the package shown in the data sheet and the SOIC package.
I'm looking at an 8 page datasheet. Perhaps there is a better datasheet or app note? What I'm looking at seems cramped and not very clear.