I'm using -MD option for GCC. This option make it to generate separate dependency file (*.d) for each source file. Also you have to inclue list of mentioned dependency files to Makefile:I'll have to have a look at how you've done that! My make file deps are manual and prone to error, not cool. I need to improve that situation. Thanks for posting about it!
OBJECTS = $(SRC:%.c=$(OBJDIR)/%.o)
DEPS = $(OBJECTS:$(OBJDIR)/%.o=$(OBJDIR)/%.d)
...
all: ...
...
-include $(DEPS)
Thank you for ignore file, I've merged it to my master.