Re: distributed computing?
Posted: Fri Jun 27, 2008 5:34 pm
During the process of formulating the ideas posted above, I considered the use of a Digital Phase Locked Loop to generate the synchronization signal. I just came across this patent:
http://patents.ic.gc.ca/cipo/cpd/en/pat ... mmary.html
It describes the use of a PLL to generate a high resolution crank angle signal, used directly for event timing, from a much lower resolution crank sensor. Basically a processor clock signal that is locked in phase and frequency with the crank.
Someday I am going to play around with this idea on a spare Prop Chip.
http://patents.ic.gc.ca/cipo/cpd/en/pat ... mmary.html
It describes the use of a PLL to generate a high resolution crank angle signal, used directly for event timing, from a much lower resolution crank sensor. Basically a processor clock signal that is locked in phase and frequency with the crank.
Someday I am going to play around with this idea on a spare Prop Chip.