Fred wrote:That is more like it! Maybe we can be friends afterall.
There are NO resistors between the 8 outputs and the CPLD inputs. The inputs are 3.3V and the outputs 5V. The software is configured to be in pullup/input mode to control these pins. In the event of the software being misconfigured to output mode again by a well meaning programmer there will be at the very least excessive heat from both cores and at the worst, both cores will lose a pin to over current.Now, the 8 control lines from the router processor also need limiting as well. But - there is simply no more room left on the board for 8 resistors. So, we are using a little trick. The HCS12 processor ports can be configured as inputs or outputs, and there are internal 50K pullup resistors (really current sources). So what is done is to run the HCS12 in "open-drain" mode. What is done is to set the output register to zero. Next, the pull ups are enabled. Then the data-direction register on the HCS12 is used to control the output. For a logic zero, the port is configured as an output, and since there is a zero in the data register the output is a zero. For a logic one, the data direction register sets the processor port as an *input*, so there is no drive - but the pullup resistors raise the output port to 5V. The pullup resistors limit the current flowing into the CPLD, and we are good.
This is what I was replying to.The ignition and control lines from the two C32 processors are 5V, and just hooking them up to the CPLD would not be good. The CPLD has internal body diodes that will sink/source current if the input is below 0 volts or above 3.3V. Feeding 5V into the 3.3V input would turn the body diodes on and without any current limiting the Altera would overheat from the free-flowing current. So, the two ignition channels from the MSII processor route thru series resistors to limit current, and to keep the risetimes short.
- Jim